The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, a lithography process uses a photomask to transfer an IC design layout pattern to a wafer substrate by an optical exposing tool (such as a stepper or a scanner). A portion of light from the exposing tool is blocked by a patterned chrome layer of the photomask to project patterned light onto a resist film deposited on the wafer substrate. The exposed resist film is then developed by a developer to form a resist pattern on the wafer substrate. Defects on the photomask, such as a pinhole in the patterned chrome layer of the photomask, pose challenges to the lithography process. For example, light can pass through the defect, such as the pinhole in the patterned chrome layer of the photomask, leading to unwanted light projected onto the resist film. An unwanted pattern is thus formed on the wafer substrate, and the wafer may be scrapped because of the unwanted pattern.
Accordingly, what is needed is a method that addresses the above issues and repairs the defect on the photomask during the photomask fabrication or the photomask allocation in a wafer fab.